• DocumentCode
    1435689
  • Title

    Low-voltage 32 Msample/s parallel pipelined switched-current ADC

  • Author

    Jonsson, B.E. ; Tenhunen, H.

  • Author_Institution
    Microelectron. X/FE, Ericsson Radio Syst. AB, Stockholm, Sweden
  • Volume
    34
  • Issue
    20
  • fYear
    1998
  • fDate
    10/1/1998 12:00:00 AM
  • Firstpage
    1906
  • Lastpage
    1907
  • Abstract
    A parallel switched-current A/D converter is presented. Eight time-interleaved switched-current ADCs operating at 4 Msample/s are used to increase the sampling rate. With channel compensation, the measured SFDR is >50 dB at 32 Msample/s with fm=1.13 MHz. The performance of this experimental design is limited by noise and a fixed-pattern timing error that is not removed by the compensation algorithm
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; compensation; parallel processing; pipeline processing; switched current circuits; 1.13 MHz; 3 V; A/D converter; LV ADC; channel compensation; compensation algorithm; fixed-pattern timing error; low-voltage operation; noise; parallel pipelined ADC; switched-current ADC; time-interleaved ADCs;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19981373
  • Filename
    722015
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1435689