A new cobalt salicide technology for 0.15-μm CMOS devices

Author

Inoue, Ken ; Mikagi, Kaoru ; Abiko, Hitoshi ; Chikaki, Shinichi ; Kikkawa, Takamoro

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan

Volume

45

Issue

11

fYear

1998

fDate

11/1/1998 12:00:00 AM

Firstpage

2312

Lastpage

2318

Abstract

A new cobalt (Co) salicide technology for sub-quarter micron CMOS transistors has been developed using high-temperature sputtering and in situ vacuum annealing. Sheet resistance of 11 Ω/□ for both gate electrode and diffusion layer was obtained with 5-nm-thick Co film. No line width dependence of sheet resistance was observed down to 0.15-μm-wide gate electrode and 0.33-μm-wide diffusion layer. The high temperature sputtering process led to the growth of epitaxial CoSi ₂ layers with high thermal stability. By using this technology 0.15 μm CMOS devices which have shallow junctions were successfully fabricated

Keywords

MOSFET; annealing; cobalt compounds; metallic epitaxial layers; semiconductor device metallisation; sputtered coatings; 0.15 micron; CMOS transistor; Co film; CoSi₂; CoSi₂ epitaxial layer; cobalt salicide technology; diffusion layer; gate electrode; high temperature sputtering; in situ vacuum annealing; shallow junction; sheet resistance; thermal stability; Annealing; CMOS technology; Cobalt; Electrodes; Ion implantation; Sputtering; Substrates; Temperature distribution; Thermal stability; Vacuum technology;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.726647

Filename

726647