Title :
Application of hardness-by-design methodology to radiation-tolerant ASIC technologies
Author :
Lacoe, Ronald C. ; Osborn, Jon V. ; Koga, Rocky ; Brown, Stephanie ; Mayer, Donald C.
Author_Institution :
Electron. & Photonics Lab., Aerosp. Corp., Los Angeles, CA, USA
fDate :
12/1/2000 12:00:00 AM
Abstract :
Radiation-hard ASIC design is enabled by the trend in commercial microelectronics toward increased radiation hardness, demonstrated here with new radiation results on a 0.25-μm commercial process utilizing shallow trench isolation. A design comparison is made between creating ASICs targeting a traditional rad-hard foundry, which may be more than two generations behind commercial foundries, applying hardness-by-design methodology at a commercial foundry, and directly targeting a commercial foundry using commercial design practices
Keywords :
application specific integrated circuits; integrated circuit design; integrated circuit technology; isolation technology; radiation hardening (electronics); 0.25 micron; hardness-by-design methodology; microelectronics; radiation hardness; radiation tolerant ASIC technology; shallow trench isolation; Application specific integrated circuits; CMOS process; CMOS technology; Foundries; Latches; Microelectronics; Microprocessors; Radiation effects; Radiation hardening; Space technology;
Journal_Title :
Nuclear Science, IEEE Transactions on
