Title :
Analysis of SET Effects in a PIC Microprocessor for Selective Hardening
Author :
Entrena, Luis ; Lindoso, Almudena ; Valderas, Mario García ; Portela, Marta ; Ongil, Celia López
Author_Institution :
Electron. Technol. Dept., Univ. Carlos III of Madrid, Leganes, Spain
fDate :
6/1/2011 12:00:00 AM
Abstract :
In this work we propose a method to evaluate the criticality of the components of a circuit with respect to Single Event Transient (SET) effects. Emulation-based fault injection is used to determine the error rate for each individual gate. The method also identifies the optimal set of flip-flops to be hardened using time redundancy techniques. The results enable the selective application of SET mitigation techniques to satisfy soft error rate requirements with reduced overheads. A PIC18 microprocessor with three different workloads has been used as a case study, and results show that just hardening 25% of gates is enough to achieve more than 99% mitigation of SET effects.
Keywords :
combinational circuits; flip-flops; logic gates; microprocessor chips; PIC18 microprocessor; SET effect analysis; emulation-based fault injection; flip-flop; selective hardening; single event transient effect; soft error rate requirement; time redundancy technique; Circuit faults; Clocks; Emulation; Field programmable gate arrays; Integrated circuit modeling; Logic gates; Random access memory; FPGA; Fault injection; single event transient; soft error;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2010.2096433
