A limit cycle suppressing arithmetic format for digital filters

Author

Bauer, Peter H. ; Ralev, Kamen R.

Author_Institution

Dept. of Electr. Eng., Notre Dame Univ., IN, USA

Volume

45

Issue

10

fYear

1998

fDate

10/1/1998 12:00:00 AM

Firstpage

1104

Lastpage

1107

Abstract

In this paper it is be shown that any digital filter with a stable transfer function can be implemented free of limit cycles, if block floating point arithmetic is used in conjunction with the so-called exponent saturation and flush-to-zero option. A certain system dependent minimum block mantissa length is required. Limit cycle suppression is achievable regardless of the structure and the quantization format. This format is simple to implement even on fixed point processors and offers high dynamic range

Keywords

digital filters; floating point arithmetic; limit cycles; block floating point arithmetic; digital filters; exponent saturation; flush-to-zero option; high dynamic range; limit cycle suppressing arithmetic format; limit cycle suppression; stable transfer function; system dependent minimum block mantissa length; Digital arithmetic; Digital filters; Digital systems; Dynamic range; Finite wordlength effects; Fixed-point arithmetic; Floating-point arithmetic; Limit-cycles; Quantization; Transfer functions;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.728865

Filename

728865