Digital Circuit Design Using Support Vector Machines

Digital circuits are preferred over its analog counterpart with the invention of microprocessors, microcontrollers, digital signal processors and Field Programmable Gate Arrays (FPGA). Digital circuits in the form of digital arithmetic and digital logics are employed for various applications. On the other side, Support Vector Machine (SVM) is considered as a state-of-the-art tool for pattern recognition. In this paper, a novel attempt is made to study, assess and design digital circuits using two-class and multi class support vector machine classifiers. It is reported in literature that computational complexity and the classification time for SVM classifier depends on the number of support vectors required for classification. In order to reduce the number of support vectors, an optimum threshold technique based SVM classifier is employed for the design of digital circuits and it is observed that a maximum of 87.5% of total support vectors are pruned on using the technique.