Realisation and implementation of a sigma-delta bitstream FIR filter

Sigma-delta signal processing or SDSP has been proposed as a method for reducing system costs by eliminating the decoding of a ΣΔ bitstream prior to processing. The design problems inherent in this are examined, and the tradeoff to the more conventional approach through the study of a bitstream FIR filter is analysed. It is found that the system imposes particular constraints on the design of the digital ΣΔ modulator used to remodulate the FIR filter output. Also, the system cost of the SDSP FIR filter is less than that for the decoded PCM Filter below a certain number of taps, currently estimated as at least 80. The design of a VLSI demonstrator that implements 16 FIR taps and remodulator, has 16-bit dynamic range and is cascadable for higher filter orders is also presented