PBTI/NBTI-Related Variability in TB-SOI and DG MOSFETs

Author

Cheng, B. ; Brown, A.R. ; Roy, S. ; Asenov, A.

Author_Institution

Dept. Electron. & Electr. Eng., Univ. of Glasgow, Glasgow, UK

Volume

31

Issue

5

fYear

2010

fDate

5/1/2010 12:00:00 AM

Firstpage

408

Lastpage

410

Abstract

We study positive bias temperature instability/negative bias temperature instability (PBTI/NBTI)-related aging-dependent statistical variability (SV) in 32-nm thin-body silicon-on-insulator (TB-SOI) and 22-nm double-gate (DG) MOSFETs using comprehensive 3-D numerical simulation. Results indicate that a high degree of PBTI/NBTI degradation can introduce a similar level of SV as the variability in the initial ??virgin?? devices introduced by random discrete dopants and line edge roughness. Simulations have shown that the TB-SOI and the DG MOSFETs have different susceptibilities to PBTI/NBTI-induced variability.

Keywords

MOSFET; numerical analysis; silicon-on-insulator; statistical analysis; DG MOSFET; PBTI-NBTI-related variability; TB-SOI; comprehensive 3D numerical simulation; double-gate MOSFET; line edge roughness; negative bias temperature instability; positive bias temperature instability; random discrete dopants; related aging-dependent statistical variability; size 32 nm; thin-body silicon-on-insulator; Double gate (DG); MOSFETs; SOI; positive bias temperature instability/negative bias temperature instability (PBTI/NBTI); statistical variability (SV);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2010.2043812

Filename

5437260