Title :
Design of dynamic pass-transistor logic circuits using 123 decision diagrams
Author :
Jaekel, Arunita ; Bandyopadhyay, Subir ; Jullien, Graham A.
Author_Institution :
VLSI Res. Group, Windsor Univ., Ont., Canada
fDate :
11/1/1998 12:00:00 AM
Abstract :
Pass transistor logic (PTL) has advantages over standard CMOS designs in terms of layout density, circuit delay, and power consumption and is well suited for pipelined circuits. In this paper we develop a decision-diagram-based model, the 123-decision diagram, which can he used to efficiently synthesize PTL circuits, and we investigate multilevel logic synthesis techniques for complex, pipelined PTL networks using this model. Experiments on a large number of benchmark circuits show that PTL networks synthesized using our techniques are significantly more economic in terms of silicon area compared to those using existing techniques
Keywords :
MOS logic circuits; binary decision diagrams; delays; integrated circuit design; logic CAD; multivalued logic circuits; 123 decision diagrams; PTL circuits; benchmark circuits; circuit delay; dynamic pass-transistor logic circuits; layout density; multilevel logic synthesis techniques; pipelined circuits; power consumption; CMOS logic circuits; Circuit synthesis; Delay; Energy consumption; Logic circuits; Logic design; Network synthesis; Power generation economics; Semiconductor device modeling; Silicon;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
