DocumentCode :
1450176
Title :
Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes
Author :
Chen, Julian Zhiliang ; Amerasekera, E. Ajith ; Duvvury, Charvaka
Author_Institution :
Mixed Signal Products, Texas Instrum. Inc., Dallas, TX, USA
Volume :
45
Issue :
12
fYear :
1998
fDate :
12/1/1998 12:00:00 AM
Firstpage :
2448
Lastpage :
2456
Abstract :
This paper describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS)-protection scheme is presented. Without requiring any additional process steps or introducing any additional impedance in signal path, the PDN-MOS is effective even for small analog/mixed-signal designs. SPICE simulations are used to optimize the design. High ESD performance of the PDNMOS protection in both nonsilicided and silicided submicron processes is demonstrated in this work
Keywords :
CMOS integrated circuits; SPICE; circuit optimisation; electrostatic discharge; integrated circuit design; protection; PDNMOS; PNP Driven NMOS; SPICE simulation; analog design; gate-driven NMOS ESD protection circuit; mixed-signal design; optimization; silicidation; submicron CMOS process; CMOS process; Design methodology; Design optimization; Electrostatic discharge; Impedance; MOS devices; Protection; SPICE; Signal design; Signal processing;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.735721
Filename :
735721
Link To Document :
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