A C-switch cell for low-voltage and high-density SRAMs

Author

Kuriyama, Hirotada ; Ishigaki, Yoshiyuki ; Fujii, Yasuhiro ; Maegawa, Shigeto ; Maeda, Shigenobu ; Miyamoto, Shouichi ; Tsutsumi, Kazuhito ; Miyoshi, Hirokazu ; Yasuoka, Akihiko

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

Volume

45

Issue

12

fYear

1998

fDate

12/1/1998 12:00:00 AM

Firstpage

2483

Lastpage

2488

Abstract

We propose a novel static random access memory (SRAM) cell named complementary-switch (C-switch) cell. The proposed SRAM cell features: (1) C-switch in which an n-channel bulk transistor and a p-channel TFT are combined in parallel; (2) single-bit-line architecture; (3) gate-all-around TFT (GAT) with large ON-current of μA order. With these three features, the proposed cell enjoys stability at 1.5 V and is 16% smaller in size than conventional cells. The C-switch cell is built with only a triple poly-Si and one metal process using 0.3 μm design rules

Keywords

SRAM chips; circuit stability; integrated circuit design; low-power electronics; memory architecture; thin film transistors; 0.3 micron; 1.5 V; C-switch cell; complementary-switch cell; design rules; gate-all-around TFT; high-density SRAM; low-voltage circuits; metal process; n-channel bulk transistor; p-channel TFT; single-bit-line architecture; stability; triple polysilicon process; Energy consumption; Equivalent circuits; Low voltage; Random access memory; SRAM chips; Stability; Thin film transistors; Timing; Ultra large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.735725

Filename

735725