Title :
A high-performance polycrystalline silicon thin film transistor with a silicon nitride gate insulator
Author :
Lee, K.H. ; Park, J.K. ; Jang, Jin
Author_Institution :
Dept. of Phys., Kyung Hee Univ., Seoul, South Korea
fDate :
12/1/1998 12:00:00 AM
Abstract :
We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiNx ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiNx and laser annealed poly-Si. After patterning thin a-Si:H/SiNx layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n+ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm2/Vs and a threshold voltage of 1 V
Keywords :
MISFET; carrier mobility; elemental semiconductors; grain size; nickel compounds; silicon; silicon compounds; thin film transistors; 1 V; 250 C; 250 nm; Ni layer deposition; NiSi silicide phase; NiSi-Si:H-SiN-Si; SiNx gate insulator; a-Si:H layer; annealing; field effect mobility; gate/source/drain electrodes; high-performance TFT; hydrogenated amorphous Si layer; laser annealed poly-Si layer; low resistance n+ poly-Si; low resistive silicide; ohmic contact; polycrystalline Si TFT; polysilicon thin film transistor; three stacked layers structure; threshold voltage; Amorphous silicon; Annealing; Contact resistance; Electrodes; Grain size; Insulation; Ohmic contacts; Silicides; Silicon compounds; Thin film transistors;
Journal_Title :
Electron Devices, IEEE Transactions on
