Maximum-likelihood based lock detectors for M-PSK carrier phase tracking loops

Carrier phase synchronisation is essential for coherent communications. Receivers typically use digital phase-locked loops (DPLLs) to acquire the carrier phase. The lock range of DPLLs, i.e. the range of frequency offsets that they can acquire, is usually significantly less than the initial frequency uncertainty in typical systems. Hence, acquisition is achieved by sweeping through the frequency uncertainty range, and stopping the sweep when the DPLL acquires the signal. Since the transmitted data symbols are in general unknown, successful acquisition is determined by a non-data aided carrier lock detector (CLD). In this reported work, a maximum-likelihood based CLD is derived which has low implementation complexity, and is better than existing CLDs while being impervious to errors in the receive Automatic Gain Control (AGC).