Title :
Fast and gate-count efficient arithmetic logic unit
Author :
Lee, Yong Surk ; Joh, P. ; You, Jae Hee ; Park, Kyu Tae
Author_Institution :
Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
fDate :
11/7/1996 12:00:00 AM
Abstract :
A CMOS arithmetic logic unit is presented with a minimum number of transistors and high speed arithmetic operations. Multiple carry chain adders and a novel 1 bit adder, are used in a carry select adder. The carry chain adder has a high degree of shared gates with a low propagation delay
Keywords :
CMOS logic circuits; adders; carry logic; logic gates; CMOS; arithmetic logic unit; carry select adder; gate-count efficiency; high speed arithmetic operations; multiple carry chain adders; propagation delay; shared gates;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961432
