A multiphase delay-locked loop with interleaving calibration

Author

Pao-Lung Chen ; Tzu-Siang Wang

Author_Institution

Dept. of Comput. & Commun. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol., Kaohsiung, Taiwan

Volume

1

fYear

2014

fDate

26-28 April 2014

Firstpage

237

Lastpage

240

Abstract

A multiphase delay-locked loop (MDLL) with interleaving calibration has been designed with TSMC 0.18 μm CMOS technology. The proposed interleaving calibration relieves the hardware cost for requirement of high resolution phase detector (PD) effectively in the conventional method with sequential calibration. In addition, the output jitter is improved because of reducing the phase transition states. The core area is 469.4 μm × 471.7 μm and power consumption is 22.6mW at 150 MHz. The measured phase error is reduced to 25ps using interleaving calibration.

Keywords

CMOS digital integrated circuits; calibration; delay lock loops; integrated circuit design; phase detectors; CMOS; TSMC; calibration; frequency 150 MHz; multiphase delay-locked loop; phase detector; power 22.6 mW; power consumption; size 0.18 mum; size 469.4 mum; size 471.7 mum; time 25 ps; Calibration; Delay lines; Delays; Detectors; Jitter; Radiation detectors; Solid state circuits; Digital to voltage convertor (DVC); Multiphase Delay-locked loop (MDLL); Sequential Calibration;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Science, Electronics and Electrical Engineering (ISEEE), 2014 International Conference on

Conference_Location

Sapporo

Print_ISBN

978-1-4799-3196-5

Type

conf

DOI

10.1109/InfoSEEE.2014.6948104

Filename

6948104