Current adjustable clock distribution network scheme for GDDR5

Author

Lim, S.-B. ; Hwang, Sunyong ; You, Jie ; Baek, Yonghyun ; Kim, Chong-Kwon

Author_Institution

Dept. of Nano-Semicond. Eng., Korea Univ., Seoul, South Korea

Volume

49

Issue

11

fYear

2013

fDate

May 23 2013

Firstpage

689

Lastpage

691

Abstract

Presented is a current adjustable clock distribution network for GDDR5. In general, GDDR5 uses a current mode logic (CML) buffer as the global driver of the clock distribution. The wide-frequency range conventional CML buffer is designed to the fastest frequency. However, the CML buffer consumes constant current at all frequencies. For this reason, the conventional buffer dissipates current more than necessary at low frequencies. A proposed current adjustable clock distribution network scheme adjusts the amount of the current consumption of the global driver according to the clock frequency. The proposed scheme is implemented in 65 nm CMOS technology, reduces power consumption by 17.7% in the wide frequency range from an average 10.26 mW of the conventional scheme to 8.44 mW.

Keywords

CMOS logic circuits; buffer circuits; clock distribution networks; current distribution; current-mode logic; driver circuits; CML buffer; CMOS technology; GDDR5; clock frequency; constant current consumption; conventional buffer current dissipation; current adjustable clock distribution network scheme; current mode logic buffer; global driver; power 10.26 mW; size 65 nm; wide-frequency range;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2012.3859

Filename

6548172