Title :
Redundancy revisited
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
Abstract :
This paper shows that when it comes to complementary metal-oxide-semiconductor (CMOS) designs undetectability does not necessarily imply redundancy. The definition of redundancy is extended to account for the special behavior encountered in CMOS designs. The accuracy of the new redundancy definition has been tested on several CMOS chips and has been found to be correct.
Keywords :
CMOS logic circuits; combinational circuits; integrated circuit design; integrated circuit testing; logic design; logic testing; redundancy; CMOS design; combinational circuit; redundancy; stuck fault; test pattern generation; undetectability; Boolean functions; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Combinational circuits; Logic design; Logic testing; Redundancy; Test pattern generators;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
