• DocumentCode
    1452908
  • Title

    Redundancy revisited

  • Author

    Savir, Jacob

  • Author_Institution
    Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
  • Volume
    6
  • Issue
    4
  • fYear
    1998
  • Firstpage
    620
  • Lastpage
    624
  • Abstract
    This paper shows that when it comes to complementary metal-oxide-semiconductor (CMOS) designs undetectability does not necessarily imply redundancy. The definition of redundancy is extended to account for the special behavior encountered in CMOS designs. The accuracy of the new redundancy definition has been tested on several CMOS chips and has been found to be correct.
  • Keywords
    CMOS logic circuits; combinational circuits; integrated circuit design; integrated circuit testing; logic design; logic testing; redundancy; CMOS design; combinational circuit; redundancy; stuck fault; test pattern generation; undetectability; Boolean functions; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Combinational circuits; Logic design; Logic testing; Redundancy; Test pattern generators;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/92.736135
  • Filename
    736135
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1452908