DocumentCode :
1452971
Title :
Algorithm-based low-power transform coding architectures: the multirate approach
Author :
Wu, An-Yeu ; Liu, K. J Ray
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Volume :
6
Issue :
4
fYear :
1998
Firstpage :
707
Lastpage :
718
Abstract :
In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes down. In this paper, we propose new algorithmic-level techniques to compensate the increased delays based on the multirate approach. We apply the technique of polyphase decomposition to design low-power transform coding architectures, in which the transform coefficients are computed through decimated low-speed input sequences. Since the operating frequency is M-times slower than the original design while the system throughput rate is still maintained, the speed penalty can be compensated at the architectural level. We start with the design of low-power multirate discrete cosine transform (DCT)/inverse discrete cosine transform (IDCT) VLSI architectures. Then the multirate low-power design is extended to the modulated lapped transform (MLT), extended lapped transform (ELT), and a unified low-power transform coding architecture. Finally, we perform finite-precision analysis for the multirate DCT architectures. The analytical results can help us to choose the optimal wordlength for each DCT channel under required signal-to-noise ratio (SNR) constraint, which can further reduce the power consumption at the circuit level. The proposed multirate architectures can also be applied to very high-speed block discrete transforms in which only low-speed operators are required.
Keywords :
VLSI; digital signal processing chips; discrete cosine transforms; integrated circuit design; low-power electronics; transform coding; DSP algorithm; discrete cosine transform; extended lapped transform; finite precision analysis; inverse discrete cosine transform; low power VLSI design; modulated lapped transform; multirate architecture; polyphase decomposition; power consumption; signal-to-noise ratio; throughput rate; transform coding; Computer architecture; Degradation; Delay; Discrete cosine transforms; Discrete transforms; Energy consumption; Frequency; Transform coding; Very large scale integration; Voltage;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.736144
Filename :
736144
Link To Document :
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