Improvement of SOI MOSFET RF Performance by Implant Optimization

Author

Chen, C.L. ; Knecht, J.M. ; Kedzierski, J. ; Chen, C.K. ; Gouker, P.M. ; Yost, D.-R. ; Healey, P. ; Wyatt, P.W. ; Keast, C.L.

Author_Institution

Lincoln Lab., Massachusetts Inst. of Technol., Lexington, MA, USA

Volume

20

Issue

5

fYear

2010

fDate

5/1/2010 12:00:00 AM

Firstpage

271

Lastpage

273

Abstract

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased by eliminating channel and drain extension implants. As a result, the f_max of the modified n-MOSFET with a 150 nm gate length exceeds 120 GHz, showing a 20% improvement over the standard MOSFET for digital circuits on the same wafer.

Keywords

CMOS integrated circuits; MOSFET; radiofrequency integrated circuits; silicon-on-insulator; breakdown voltage; digital circuits; foundry fabrication; implant optimization; output resistance; silicon on insulator MOSFET RF performance; transconductance; Fully depleted silicon on insulator (FDSOI); RF MOSFET; mixed-signal CMOS; silicon on insulator (SOI);

fLanguage

English

Journal_Title

Microwave and Wireless Components Letters, IEEE

Publisher

ieee

ISSN

1531-1309

Type

jour

DOI

10.1109/LMWC.2010.2045586

Filename

5438872