A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

Author

Anand, Seema Butala ; Razavi, Behzad

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

36

Issue

3

fYear

2001

fDate

3/1/2001 12:00:00 AM

Firstpage

432

Lastpage

439

Abstract

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2⁷-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm²

Keywords

CMOS analogue integrated circuits; integrated circuit noise; integrated optoelectronics; jitter; low-power electronics; optical receivers; phase locked loops; phase noise; sample and hold circuits; synchronisation; 0.4 micron; 2.5 Gbit/s; 3.3 V; 33.5 mW; CMOS clock recovery circuit; NRZ data; PRBS sequence; excess phase technique; linear phase detectors; nonlinear phase detectors; phase noise; power dissipation; rms jitter; sample-and-hold phase detector; total power; two-stage ring oscillator; CMOS digital integrated circuits; CMOS technology; Clocks; Detectors; Jitter; Optical signal processing; Phase detection; Phase noise; Power dissipation; Ring oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.910482

Filename

910482