A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%

Author

Yokoyama, Yuji ; Itoh, Nobutaka ; Hasegawa, Masatoshi ; Katayama, Masahiro ; Akasaki, Hiroshi ; Kaneda, Masayuki ; Ueda, Toshitsugu ; Tanaka, Yousuke ; Yamasaki, Eiji ; Todokoro, Masaya ; Toriyama, Keinosuke ; Miki, Hiroshi ; Yagyu, Masayoshi ; Takashima,

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

Volume

36

Issue

3

fYear

2001

fDate

3/1/2001 12:00:00 AM

Firstpage

503

Lastpage

509

Abstract

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access time and memory-cell area efficiency of 33% has been successfully developed with a single-side interface architecture, high-speed circuit design, and low-voltage design. In the high-speed circuit design, a multiword redundancy scheme and Y-select merged sense scheme are developed to achieve the performance goal. In the low-voltage design, a dual-complement charge-pump scheme and a decoupling capacitor utilizing a tantalum-oxide capacitor are developed to retain high performance at low supply voltage

Keywords

DRAM chips; cellular arrays; high-speed integrated circuits; low-power electronics; memory architecture; redundancy; 1.8 V; 18 Mbit; 33 percent; 9 ns; DRAM macro; RAS access time; Y-select merged sense scheme; decoupling capacitor; dual-complement charge-pump scheme; high-speed circuit design; low-voltage design; memory-cell area efficiency; multiword redundancy scheme; row-address-strobe access time; single-side interface architecture; supply voltage; Bandwidth; Capacitors; Charge pumps; Circuit synthesis; High speed integrated circuits; Integrated circuit noise; Latches; Low voltage; Random access memory; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.910489

Filename

910489