DocumentCode
1453583
Title
5.5-V I/O in a 2.5-V 0.25-μm CMOS technology
Author
Annema, Anne-Johan ; Geelen, Govert J G M ; De Jong, Peter C.
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
Volume
36
Issue
3
fYear
2001
fDate
3/1/2001 12:00:00 AM
Firstpage
528
Lastpage
538
Abstract
A robust high-voltage-tolerant I/O that does not need process options is presented, demonstrated on 5.5-V-tolerant I/O in a 2.5-V 0.25-μm CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation. Measurements on realized circuits, under accelerated stress conditions, indicate an extrapolated lifetime of hundreds of years for 5.5-V pad voltage swing, 2.2-V supply voltage. The shown concepts can easily be scaled toward newer processes or other interfacing voltages
Keywords
CMOS integrated circuits; buffer circuits; high-voltage techniques; hot carriers; integrated circuit reliability; 0.25 micron; 2.5 V; 5.5 V; CMOS integrated circuit; I/O buffer circuit; high voltage tolerance; hot carrier degradation; lifetime; oxide stress; reliability; Acceleration; CMOS process; CMOS technology; Costs; Degradation; Hot carriers; Integrated circuit measurements; Robustness; Stress measurement; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.910493
Filename
910493
Link To Document