Title :
An improved method to correlate measured circuit speed with simulation [CMOS gate arrays]
Author :
Krieger, Gadi ; Cuevas, Peter P. ; Misheloff, Mike N. ; Spadea, Gregorio
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
fDate :
9/1/1990 12:00:00 AM
Abstract :
The relationship between the measured propagation delay of elementary circuits and the values obtained by circuit SPICE modeling was studied. Systematic and random variations of Leff of the actual circuit from the modeled values Leff, which were extracted from separate test devices, were identified as a major source of error. The error was significantly reduced by an improved method to obtain the values of Leff within the logic circuits, thus permitting accurate circuit performance modeling and the required technology optimization
Keywords :
CMOS integrated circuits; circuit analysis computing; delays; integrated logic circuits; logic CAD; logic arrays; CMOS gate array circuits; circuit SPICE modeling; circuit performance modeling; circuit speed; elementary circuits; error; logic circuits; measured propagation delay; random variations; simulation; systematic variations; technology optimization; test devices; CMOS logic circuits; Circuit simulation; Circuit testing; Delay; Design optimization; Integrated circuit modeling; Logic circuits; Ring oscillators; Semiconductor device modeling; Velocity measurement;
Journal_Title :
Electron Devices, IEEE Transactions on
