Scheduling for input-queued packet switches by a re-configurable parallel match evaluator

Author

Beldianu, Spiridon F. ; Rojas-Cessa, Roberto ; Oki, Eiji ; Ziavras, Sotirios G.

Author_Institution

Dept. of Electr. & Comp. Eng., New Jersey Inst. of Technol., Newark, NJ, USA

Volume

14

Issue

4

fYear

2010

fDate

4/1/2010 12:00:00 AM

Firstpage

357

Lastpage

359

Abstract

A parallel match evaluator (PE) selects the most productive match for an input-queued (IQ) switch among several tested. However, current PE-based approaches use N fixed permutations out of possible N!, where N is the number of switch ports. A fixed permutation represents a permanent match between the inputs and outputs. To improve switching performance, this letter proposes a re-configurable PE (RPE) where permutations are selected according to traffic pattern, queue occupancy, or queuing times. This letter shows the performance improvement achieved with the proposed RPE.

Keywords

packet switching; queueing theory; scheduling; input-queued packet switches; packet scheduling; permutation; queue occupancy; queuing times; reconfigurable parallel match evaluator; switch ports; traffic pattern; Counting circuits; Fabrics; Impedance matching; Packet switching; Switches; Testing; Throughput; Traffic control; Scheduling, maximal matching, input-queued switch, match evaluator;

fLanguage

English

Journal_Title

Communications Letters, IEEE

Publisher

ieee

ISSN

1089-7798

Type

jour

DOI

10.1109/LCOMM.2010.04.092440

Filename

5439364