Cascade adaptive speed control of a thyristor-driven DC motor

A cascade speed control strategy for a thyristor driven DC motor subjected to parameter variations is proposed. A dual mode adaptive inner current loop is cascaded with a model reference adaptive speed control loop. The scheme is implemented in a 16 bit microcomputer using a floating point coprocessor. Tests on a DC machine have been conducted. The proposed solution guarantees a stable and predefined performance under all operating conditions. Comparisons with a conventional analog speed control are made.