• DocumentCode
    145651
  • Title

    Direct measurement of ingress and egress latency on 1000Base-T Gigabit Ethernet links

  • Author

    Noseworthy, Bob

  • Author_Institution
    InterOperability Lab., Univ. of New Hampshire, Durham, NH, USA
  • fYear
    2014
  • fDate
    22-26 Sept. 2014
  • Firstpage
    53
  • Lastpage
    58
  • Abstract
    Any error in a physical layer´s asymmetry corrections for egress and ingress latency can result in uncorrectable timing error. These asymmetries increase the timing inaccuracy of any PTP system. A technique to directly measure the ingress and egress latencies of a 1000Base-T Gigabit Ethernet physical layer is presented.
  • Keywords
    local area networks; protocols; synchronisation; Ethernet links; Ethernet physical layer; PTP system; egress latency; ingress latency; physical layer asymmetry corrections; precision time protocol; timing error; Accuracy; Clocks; Delays; Hardware; Physical layer; Transmitters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS), 2014 IEEE International Symposium on
  • Conference_Location
    Austin, TX
  • Print_ISBN
    978-1-4799-2698-5
  • Type

    conf

  • DOI
    10.1109/ISPCS.2014.6948531
  • Filename
    6948531
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=145651