Title :
Through Silicon Via Reliability
Author :
Cassidy, Cathal ; Kraft, Jochen ; Carniello, Sara ; Roger, Frederic ; Ceric, Hajdin ; Singulani, Anderson Pires ; Langer, Erasmus ; Schrank, Franz
Author_Institution :
austriamicrosystems AG, Unterpremstaetten, Austria
fDate :
6/1/2012 12:00:00 AM
Abstract :
Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introduced, and key parameters for reliability assessment, such as residual stress, resistance, leakage, and dielectric breakdown, are discussed. Reliability data are presented, including the characterization of TSV parameters as a function of various accelerated lifetime stress tests, as well as assessments of the density and impact of TSV manufacturing defects. The presented data demonstrate that while the TSV is inherently quite robust, latent manufacturing defects pose a significant risk to long-term reliability. Screening methodologies, defect modes, failure analysis methods, process improvement, and correspondingly improved defect density results are discussed. The results are considered pertinent to the development and reliability of novel 3-D integrated process technologies.
Keywords :
failure analysis; integrated circuit interconnections; integrated circuit reliability; three-dimensional integrated circuits; 3D integrated process technology; TSV manufacturing defects; dielectric breakdown; fabrication technology; failure analysis method; geometry; interconnections; leakage; process improvement; residual stress; resistance; semiconductor technology; through-silicon via reliability; vertical integration; Current measurement; Reliability; Resistance; Silicon; Stress; Through-silicon vias; Dielectric breakdown; reliability; three-dimensional integrated circuits; through silicon vias (TSVs);
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2012.2189212