Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Author

Rahmati, D. ; Murali, S. ; Benini, Luca ; Angiolini, Federico ; De Micheli, G. ; Sarbazi-Azad, H.

Author_Institution

Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran

Volume

62

Issue

3

fYear

2013

fDate

Mar-13

Firstpage

452

Lastpage

467

Abstract

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst case bandwidth and latency bounds for RT traffic streams on wormhole-switched NoCs with arbitrary topology. The proposed methods apply to best-effort NoC architectures, with no extra hardware dedicated to RT traffic support. By applying our methods to several realistic NoC designs, we show substantial improvements (more than 30 percent in bandwidth and 50 percent in latency, on average) in bound tightness with respect to existing approaches.

Keywords

embedded systems; integrated circuit design; network topology; network-on-chip; RT traffic streams; accurate performance bounds; arbitrary topology; best effort network-on-chip; complex embedded applications; latency bounds; real-time communication support; wormhole-switched NoC; worst case bandwidth; Bandwidth; Delay; Hardware; Mathematical model; Quality of service; Real time systems; Registers; NoC; QoS; SoC; analytical model; best-effort analysis; performance; real time; wormhole switching;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.2011.240

Filename

6109240