• DocumentCode
    146108
  • Title

    Effects of constant voltage stress on organic complementary logic inverters

  • Author

    Wrachien, N. ; Cester, A. ; Lago, N. ; Meneghesso, Gaudenzio ; D´Alpaos, R. ; Stefani, A. ; Turatti, G. ; Muccini, M.

  • Author_Institution
    Dept. of Inf. Eng., Univ. of Padova, Padua, Italy
  • fYear
    2014
  • fDate
    22-26 Sept. 2014
  • Firstpage
    298
  • Lastpage
    301
  • Abstract
    We subjected all-organic complementary inverters to constant voltage stress. We found a 20% maximum variation of DC inverter parameters after a 104-s stress. The largest degradation was in the delay times, which increase up to a factor 7. This is due to the threshold voltage variation in pTFTs and the mobility reduction in nTFTs.
  • Keywords
    logic gates; thin film transistors; DC inverter parameters; all-organic complementary inverters; constant voltage stress; mobility reduction; nTFT; organic complementary logic inverters; organic thin-film-transistors; pTFT; threshold voltage variation; Degradation; Inverters; Logic gates; Organic thin film transistors; Stress; Threshold voltage; complementary inverters; organic TFT;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference (ESSDERC), 2014 44th European
  • Conference_Location
    Venice
  • ISSN
    1930-8876
  • Print_ISBN
    978-1-4799-4378-4
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2014.6948819
  • Filename
    6948819
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=146108