Networks on chip design for real-time systems

The paper presents a new design methodology of a customized and distributed network on chip (NoC) that efficiently deals with either real-time or high throughput systems. Our previous work [1] efficiently transforms a complex VLSI system into a number of distributed subsystems. The functional decomposition was achieved thanks to a judicious task assignment so that the tasks that strongly communicate with each other are assigned to the same subsystem. Such an assignment addresses the issue of bus-conflict while considering the bandwidth, area and power dissipation constraints. Then, a customized NoC is designed for each subsystem so that to avoid the hop count problem as well as the contention one while routing the packets from the source to the sink nodes.