A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converter

This paper presents a 10-bit all binary-weighted current-steering digital-to-analog converter (DAC) with low-glitch and low-power properties. Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS process, and dissipates 19mW from a single 1.8V power supply.