Finite state machine encoding for VHDL synthesis

Finite state machine (FSM) optimisation has usually been studied through state assignment, state vector encoding, and combinational logic optimisation. Such details should not be consequential in behavioural descriptions. On the other hand, describing correct and efficient hardware structures in VHDL (VHSIC hardware description language), or generally in any high-level description language, is more a question of description style than correct language statements. Therefore, more or less conscious choices are made in the design description itself that guide the synthesis software toward a specific implementation. The best implementation is also dependent on the target technology and, therefore, there is no single best description style for all FSMs. The paper is a study of the kind of performance trade-offs that can be made by changing the description style. A program is shown to be able to generate these different descriptions from an intermediate format (kiss2) describing the FSM. Therefore, this process for finding a better description could be automated and performed by the synthesis software itself. Descriptions are tested on a set of 13 FSMs most from a benchmark suite LGSynth3. The results show at least two times better performance of speed or area in the best description compared with the worst. In performance critical applications this difference can be of a crucial importance