DocumentCode :
1463595
Title :
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic
Author :
Abdel-Hafeez, Saleh ; Gordon-Ross, Ann
Author_Institution :
Dept. Comput. Eng., Jordan Univ. of Sci. & Technol. Coll. of IT, Irbid, Jordan
Volume :
19
Issue :
6
fYear :
2011
fDate :
6/1/2011 12:00:00 AM
Firstpage :
1023
Lastpage :
1033
Abstract :
We present a high-speed wide-range parallel counter that achieves high operating frequencies through a novel pipeline partitioning methodology (a counting path and state look-ahead path), using only three simple repeated CMOS-logic module types: an initial module generates anticipated counting states for higher significant bit modules through the state look-ahead path, simple D-type flip-flops, and 2-bit counters. The state look-ahead path prepares the counting path´s next counter state prior to the clock edge such that the clock edge triggers all modules simultaneously, thus concurrently updating the count state with a uniform delay at all counting path modules/stages with respect to the clock edge. The structure is scalable to arbitrary N-bit counter widths (2-to-2N range) using only the three module types and no fan-in or fan-out increase. The counter´s delay is comprised of the initial module access time (a simple 2-bit counting stage), one three-input and-gate delay, and a D-type flip-flop setup-hold time. We implemented our proposed counter using a 0.15-μ m TSMC digital cell library and verified maximum operating speeds of 2 and 1.8 GHz for 8- and 17-bit counters, respectively. Finally, the area of a sample 8-bit counter was 78 125 μ m2 (510 transistors) and consumed 13.89 mW at 2 GHz.
Keywords :
CMOS logic circuits; counting circuits; flip-flops; logic partitioning; CMOS logic module; D-type flip-flops; TSMC digital cell library; counting path; digital CMOS parallel counter architecture; pipeline partitioning methodology; power 13.89 mW; size 0.15 mum; state look ahead logic; uniform delay; CMOS logic circuits; Clocks; Counting circuits; Decoding; Delay effects; Design methodology; Flip-flops; Frequency; Pipelines; Propagation delay; Architecture design; high-performance counter design; parallel counter design; pipeline counter design;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2010.2044818
Filename :
5443645
Link To Document :
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