• DocumentCode
    1465845
  • Title

    A new synchronizer design

  • Author

    Walker, Jacqueline ; Cantoni, Antonio

  • Author_Institution
    Australian Telecom. Res. Inst., Curtin Univ. of Technol., Bentley, WA, Australia
  • Volume
    45
  • Issue
    11
  • fYear
    1996
  • fDate
    11/1/1996 12:00:00 AM
  • Firstpage
    1308
  • Lastpage
    1311
  • Abstract
    A new synchronizer design is presented. Current synchronizer designs have certain disadvantages, both in characterization and in the tradeoff between settling time and sampling rate, which are overcome in the new design. Two possible implementations of the synchronizer are discussed
  • Keywords
    asynchronous circuits; logic design; signal processing; synchronous digital hierarchy; sampling rate; settling time; synchronizer design; Broadcasting; Degradation; Digital systems; Distributed computing; Fault diagnosis; Fault tolerance; Hypercubes; Proposals; Routing; Signal design;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.544488
  • Filename
    544488
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1465845