Title :
Fast, minimal decoding complexity, systematic (13, 8) single-error-correcting codes for on-chip DRAM applications
Author_Institution :
Inst. d´´Electron. Fondamentale, Univ. de Paris-Sud, Orsay, France
fDate :
3/29/2001 12:00:00 AM
Abstract :
Fast, minimal decoding complexity (13,8) binary systematic single-error-correcting codes are proposed for on-chip DRAM applications. These (13,8) codes allow fast single error correcting with one extra parity bit penalty and can be used in combinational circuits with minimal (ultimate) decoding complexity
Keywords :
DRAM chips; circuit complexity; combinational circuits; decoding; error correction codes; combinational circuits; fast single error correction; minimal decoding complexity; onchip DRAM applications; single-error-correcting codes; systematic (13, 8) single ECCs;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010316
