• DocumentCode
    1467397
  • Title

    Multiple target clock distribution with arbitrary delay interconnects

  • Author

    Aguiar, R.L. ; Santos, D.M.

  • Author_Institution
    Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
  • Volume
    34
  • Issue
    22
  • fYear
    1998
  • fDate
    10/29/1998 12:00:00 AM
  • Firstpage
    2119
  • Lastpage
    2120
  • Abstract
    A new technique is presented for multiple target clock distribution using controlled delay lines. This method is demonstrated to work with arbitrary delay lines. Simulations show that this method has strong advantages for cluster-level clock distribution, and can be applied to multichip interconnections
  • Keywords
    CMOS digital integrated circuits; delay lines; integrated circuit interconnections; multichip modules; timing; CMOS ICs; MCM; cluster-level clock distribution; controlled delay lines; delay interconnects; multichip interconnections; multiple target clock distribution;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19981520
  • Filename
    741320
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1467397