Design and simulation of digital frequency meter using VHDL

The main aim of this paper is to design the digital frequency meter with frequency analyzing module. As a measuring frequency´s instrument, the cymometer often refer to as electronic counter in modern electronic technology. Its basic function is to measure the signal frequency and this frequency counter has a wide range of applications. It is not only used in the general simple instrument´s measurement, but also used in teaching, research, high-precision instruments measuring, industrial control and other areas. Currently, the high-performance and simple-structure electronic products have become the mainstay of market. In this project the cymometer not only measure the frequency but also determines the jitter, glitches status etc., Digital Frequency Meter were designed using VHDL language and simulated using Modelsim 6.3v simulator. In order to increase the efficiency of the system, sleep mode concept is introduced, which reduces unwanted circuit power utilization.