DocumentCode
146945
Title
Run-time reconfiguration of Processing Elements through soft-core processor
Author
Nithya, R. ; Sarath Chandran, K.R. ; Chandramani, V. Premanand
Author_Institution
Dept. of Electron. & Commun. Eng., SSN Coll. of Eng., Chennai, India
fYear
2014
fDate
3-5 April 2014
Firstpage
813
Lastpage
817
Abstract
This paper proposes a system-on-chip design to perform run-time reconfiguration using soft-core processor. The reconfigurable module consists of a set of Processing Elements (PEs) that are fully connected to each other through a crossbar network. Run-time reconfiguration is achieved by dynamically selecting the desired number of PEs based on the input data set through soft-core processor. This dynamic selection of PEs leads to optimum resource utilization and lesser power consumption for computationally intensive applications such as media processing. Optimization was achieved through minimizing number of logic elements, total fan-out, and total power dissipation for systems with varying number of processing elements.
Keywords
integrated circuit design; logic design; microprocessor chips; power consumption; system-on-chip; crossbar network; logic elements; media processing; power consumption; processing elements run-time reconfiguration; soft-core processor; system-on-chip design; Adders; Hardware; Inverters; Media; Registers; Silicon; System-on-chip; Nios II; Processing elements; Reconfigurable architectures; Run Time reconfiguration; Soft core processors; System-on-Chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications and Signal Processing (ICCSP), 2014 International Conference on
Conference_Location
Melmaruvathur
Print_ISBN
978-1-4799-3357-0
Type
conf
DOI
10.1109/ICCSP.2014.6949956
Filename
6949956
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