A Low-Jitter Synchronous Clock Distribution Scheme Using a DAC Based PLL

Author

Wu, Jie ; Ma, Yichao ; Zhang, Jie ; Xie, Mingpu

Author_Institution

Dept. of Modern Phys., Univ. of Sci. & Technol. of China, Hefei, China

Volume

57

Issue

2

fYear

2010

fDate

4/1/2010 12:00:00 AM

Firstpage

589

Lastpage

594

Abstract

A low-jitter clock is essential to achieve high performance in a large scale system of distributed sensors. We propose to use a low cost DAC, VCXO and FPGA counter to generate distributed synchronous clocks. The new system called digital distributed synchronous clock (DDSC) can reduce the jitter to 14.6 ps, a 60% reduction from 36.5 ps in a traditional PLL. When these two clocks are used as the source for a 24-bit ADC system, the result shows that DDSC makes the total harmonic distortion (THD) decrease dramatically from -106 dB with PLL to -117 dB.

Keywords

analogue-digital conversion; clock distribution networks; digital-analogue conversion; distributed sensors; field programmable gate arrays; harmonic distortion; jitter; phase locked loops; ADC system; DAC Based PLL; DDSC; FPGA counter; THD; VCXO; digital distributed synchronous clocks; distributed sensors; large scale system; low-jitter synchronous clock distribution scheme; total harmonic distortion; Clocks; Costs; Counting circuits; Field programmable gate arrays; Jitter; Large-scale systems; Phase locked loops; Sensor systems; Synchronous generators; Total harmonic distortion; Distributed clock; low jitter; phase locked loops; synchronization;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2009.2037321

Filename

5446508