DocumentCode :
1470578
Title :
Digital model for switching transistors in series-gated ECL
Author :
Choy, C.S. ; Ho, C.Y.
Author_Institution :
Dept. of Electron., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Volume :
25
Issue :
13
fYear :
1989
fDate :
6/22/1989 12:00:00 AM
Firstpage :
866
Lastpage :
867
Abstract :
A digital model is proposed that allows function verification and timing analysis of series-gated ECL to be performed on a logic simulation. Traditionally, an analogue simulator will be necessary because series-gated ECL circuits are constructed from transistors rather than primitive gates. The model is meant to replace each switching transistor in a series-gated ECL. A simulation time at least two magnitudes lower has bean achieved.
Keywords :
bipolar integrated circuits; circuit analysis computing; digital simulation; emitter-coupled logic; integrated logic circuits; logic CAD; digital model; function verification; logic simulation; series-gated ECL; simulation time; switching transistors; timing analysis;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19890583
Filename :
91810
Link To Document :
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