DocumentCode
1473547
Title
ESTA: an expert system for DFT rule verification
Author
Camurati, P. ; Gianoglio, P. ; Gianoglio, R. ; Prinetto, P.
Author_Institution
Turin Polytech., Italy
Volume
7
Issue
11
fYear
1988
fDate
11/1/1988 12:00:00 AM
Firstpage
1172
Lastpage
1180
Abstract
A description is given of ESTA, an expert system for the automation of design for testability (DFT) verification. The system takes descriptions written in a conventional hardware description language as input, translates them into a intermediate Prolog form and checks whether they comply either with the level sensitive scan design (LSSD) DFT method of B. Eichelberger and T.W. Williams (1977) or the built-in logic block observation (BILBO) DFT techniques of B. Konemann et al. (1979)
Keywords
VLSI; circuit CAD; expert systems; logic CAD; BILBO; CAD; DFT rule verification; ESTA; LSSD; built-in logic block observation; computer aided design; design for testability; digital ICs; expert system; hardware description language; intermediate Prolog form; level sensitive scan design; Artificial intelligence; Automatic testing; Circuit testing; Design automation; Design for testability; Emulation; Expert systems; Humans; System testing; Very large scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.9187
Filename
9187
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