Title :
A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity
Author :
Kyung, Kye-Hyun ; Lee, Hi-Choon ; Song, Ki-Whan ; Song, Ho-Sung ; Jung, Keewook ; Moon, Joon-Seo ; Kim, Byoung-Sul ; Cho, Sung-Bum ; Kim, Changhyun ; Cho, Soo-In
Author_Institution :
Div. of Memory Product & Technol., Samsung Electron. Co., Kyungki, South Korea
fDate :
5/1/2001 12:00:00 AM
Abstract :
A 2.5-V 288-Mb packet-based DRAM with 32 banks and 18-DQ organization architecture achieving a peak bandwidth of 2.0-GB/s at V DD=2.25 V and T=100°C has been developed using (1) an area- and performance-efficient chip architecture with a mixture of high-speed interface circuits with DRAM peripheral circuits to increase cell efficiency; (2) a multilevel controlled bitline equalizing scheme and a distributed sense amplifier driving scheme to enhance DRAM core timing margin while increasing the number of cells per wordline for cell efficiency over the previous subwordline driving scheme; (3) a flexible column redundancy scheme with multiple fuse boxes instead of excessive spare memory cell arrays for 143 internal I/O architecture; and (4) optimized I/O circuits and pin parasitic design including pad and package to maximize the operating frequency
Keywords :
CMOS memory circuits; DRAM chips; cellular arrays; equalisers; high-speed integrated circuits; redundancy; 100 degC; 2.0 Gbyte/s; 2.5 V; 288 Mbit; CMOS; DRAM peripheral circuits; cell efficiency; core timing margin; distributed sense amplifier driving scheme; flexible column redundancy scheme; high-speed interface circuits; multilevel controlled bitline equalizing scheme; multiple fuse boxes; noise immunity; operating frequency; optimized I/O circuits; packet-based DRAM; performance-efficient chip architecture; pin parasitic design; Bandwidth; Current control; Design optimization; Distributed amplifiers; Flexible printed circuits; Frequency; Fuses; Packaging; Random access memory; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
