Ta/sub 2/O/sub 5//silicon barrier height measured from MOSFETs fabricated with Ta/sub 2/O/sub 5/ gate dielectric

Author

Lai, Benjamin Chihming ; Yu, Jing-Chi ; Lee, Joseph Ya-min

Author_Institution

Dept. of Electr. Eng., Tsinghua Univ., Beijing, China

Volume

22

Issue

5

fYear

2001

fDate

5/1/2001 12:00:00 AM

Firstpage

221

Lastpage

223

Abstract

N-channel metal oxide semiconductor field effect transistors with Ta/sub 2/O/sub 5/ gate dielectric were fabricated. The Ta/sub 2/O/sub 5//silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I/sub g//I/sub d/) versus ln(I/sub sub//I/sub d/) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta/sub 2/O/sub 5/ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V.

Keywords

MOSFET; dielectric thin films; elemental semiconductors; hot carriers; impact ionisation; semiconductor device measurement; semiconductor device models; semiconductor-insulator boundaries; silicon; tantalum compounds; thermionic emission; 0.77 eV; 2 V; NMOSFET; Ta/sub 2/O/sub 5/ gate dielectric; Ta/sub 2/O/sub 5/-Si; Ta/sub 2/O/sub 5//Si barrier height; field effect transistors; impact ionization energy; low supply voltage; lucky electron model; n-MOSFETs; n-channel MOSFET; thermionic emission model; Dielectric measurements; Dielectric substrates; Electron emission; Hot carriers; Impact ionization; MOSFETs; Optical films; Semiconductor device modeling; Silicon; Thermionic emission;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.919235

Filename

919235