• DocumentCode
    1475498
  • Title

    Implementation issues of the two-level residue number system with pairs of conjugate moduli

  • Author

    Skavantzos, Alexander ; Abdallah, Mohammad

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
  • Volume
    47
  • Issue
    3
  • fYear
    1999
  • fDate
    3/1/1999 12:00:00 AM
  • Firstpage
    826
  • Lastpage
    838
  • Abstract
    One of the most important considerations when designing residue number systems (RNSs) is the choice of the moduli set; this is due to the fact that the dynamic range of the system, its speed, as well as its hardware complexity, depend on both the forms as well as the number of moduli chosen; In this paper, a new class of multimoduli RNSs based on sets of forms {2n(1)-1, 2n(1)+1, 2n2-1, 2n(2)+1, ···, 2n(L)-1, 2n(L)+1} is presented. The moduli 2n(i)-1 and 2 n(i)+1 are called conjugates of each other. The new RNSs that rely on pairs of conjugate moduli result in hardware-efficient two-level implementations for the weighted-to-RNS and RNS-to-weighted conversions, achieve very large dynamic ranges, and imply fast and efficient RNS processing. When compared with conventional systems of the same number of moduli and the same dynamic range, the proposed new systems offer the following benefits: (1) hardware savings of 25 to 40% for the weighted-to-RNS conversion and (2) a reduction of over 80% in the complexity of the final Chinese remainder theorem (CRT) involved in the RNS-to-weighted conversion. Thus, significant compromises between large dynamic ranges, fast internal processing, and low complexity are achieved by the new systems
  • Keywords
    computational complexity; residue number systems; Chinese remainder theorem; RNS-to-weighted conversions; conjugate moduli; dynamic range; hardware complexity; implementation issues; internal processing; moduli set; multimoduli RNS; two-level residue number system; weighted-to-RNS conversion; Application specific processors; Cathode ray tubes; Computer architecture; Digital arithmetic; Dynamic range; Error correction; Fault tolerance; Hardware; Helium; Process design;
  • fLanguage
    English
  • Journal_Title
    Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1053-587X
  • Type

    jour

  • DOI
    10.1109/78.747787
  • Filename
    747787