DocumentCode :
1476702
Title :
Logic synthesis for engineering change
Author :
Chih-Chang Lin ; Kuang-Chien Chen ; Marek-Sadowska, M.
Author_Institution :
VerPlex Syst. Inc., Santa Clara, CA, USA
Volume :
18
Issue :
3
fYear :
1999
fDate :
3/1/1999 12:00:00 AM
Firstpage :
282
Lastpage :
292
Abstract :
During the process of very large scale integration design, specifications are often changed. To preserve as large a portion of the engineering effort as possible, it is desirable that such changes will not lead to a very different design. In this work, we consider logic synthesis algorithms for handling engineering changes. To solve it, we propose a combination of multiple-error diagnosis and logic minimization techniques. Given a new specification and an existing synthesized network, our algorithms first identify the candidate signals in the network, and then synthesize the candidate functions. The synthesis step utilizes the existing network as much as possible so that the new specification can be realized with minimal changes.
Keywords :
Boolean functions; VLSI; automatic test pattern generation; binary decision diagrams; circuit CAD; digital integrated circuits; integrated circuit design; logic CAD; minimisation of switching nets; CAD; VLSI design; design specifications; engineering changes; logic minimization techniques; logic synthesis algorithms; multiple-error diagnosis; very large scale integration; Automatic logic units; Automatic test pattern generation; Design engineering; Logic testing; Minimization; Network synthesis; Power engineering and energy; Signal processing; Signal synthesis; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.748158
Filename :
748158
Link To Document :
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