Title :
Differentially-tuned low-spur PLL using 65 nm CMOS process
Author :
Yun, S.-J. ; Lee, Hwi Don ; Kim, K.-D. ; Kwon, J.-K.
Author_Institution :
ETRI (Electron. & Telecommun. Res. Inst.), Daejeon, South Korea
Abstract :
A differentially-tuned LC-VCO PLL using a transformer-resonator and a loop-phase control scheme is proposed. The phase of a control path between the differential controls is adjusted to suppress spurious tones. The measured results for the proposed PLL, implemented in a CMOS 65 nm process, show operation frequencies of 3.5-5.6 GHz, phase noise of -118.5 dBc/Hz at 1 MHz offset, and spur rejection of 73 dB, while dissipating 3.2 mA at 1 V supply.
Keywords :
CMOS digital integrated circuits; field effect MMIC; microwave oscillators; phase locked loops; phase noise; voltage-controlled oscillators; CMOS process; LC-VCO PLL; differential controls; differentially-tuned PLL; frequency 3.5 GHz to 5.6 GHz; loop-phase control; low-spur PLL; phase noise; size 65 nm; transformer resonator; voltage 1 V;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2011.0166
