DocumentCode
1477040
Title
Fuzzy-based CMOS circuit partitioning in built-in current testing
Author
Tseng, Wang-Dauh ; Wang, Kuochen
Author_Institution
Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
7
Issue
1
fYear
1999
fDate
3/1/1999 12:00:00 AM
Firstpage
116
Lastpage
120
Abstract
We propose a fuzzy-based approach which provides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing (BICT). Experimental results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning in comparison with other approaches with a fixed threshold, and a better module size can thus be determined to reflect a change of circuit properties.
Keywords
CMOS logic circuits; built-in self test; fuzzy systems; integrated circuit testing; logic partitioning; logic testing; BICT partitioning; CMOS circuit partitioning; built-in current testing; circuit properties; design space; fuzzy-based approach; module size; soft threshold; Circuit faults; Circuit noise; Circuit optimization; Circuit testing; Clocks; Costs; Current measurement; Delay; Packaging; Voltage;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.748207
Filename
748207
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