• DocumentCode
    1477611
  • Title

    Fault models and tests for a 2-bit-per-cell MLDRAM

  • Author

    Redeker, Michael ; Cockburn, Bruce F. ; Elliott, Duncan G.

  • Author_Institution
    Philips Semicond. AG, Zurich, Switzerland
  • Volume
    16
  • Issue
    1
  • fYear
    1999
  • Firstpage
    22
  • Lastpage
    31
  • Abstract
    Multilevel DRAM technology may become a cost effective way to increase semiconductor memory storage density. The authors develop an MLDRAM fault model using both manual analysis and analog simulation. They also propose several alternative testing strategies and possible design-for-testability enhancements
  • Keywords
    DRAM chips; circuit simulation; design for testability; fault simulation; integrated circuit testing; 2-bit-per-cell MLDRAM; MLDRAM fault model; alternative testing strategies; analog simulation; design-for-testability enhancements; fault models; manual analysis; multilevel DRAM technology; semiconductor memory storage density; Capacitance; Circuits; Encoding; Random access memory; Semiconductor device noise; Semiconductor device testing; Semiconductor memory; Signal processing; Switches; Voltage;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.748802
  • Filename
    748802
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1477611