Second-degree digital differentiator-based power system frequency estimation under non-sinusoidal conditions

This study presents development and implementation of a novel digital signal processing algorithm for on-line estimation of the fundamental frequency of non-sinusoidal power system signals. The basic algorithm relies on the development of a new variance reduction algorithm and design of an optimised infinite impulse response (IIR) second-degree digital differentiator (SDDD). The design of SDDD consists of obtaining a second-degree integrator from Tick integrator, and then modifying and optimising its transfer function appropriately to attain a stable second-degree differentiator. Compared with the well-established technique such as the enhanced phase-locked-loop (EPLL) system, the proposed algorithm provides faster transient response, higher degree of immunity and insensitivity to harmonics and noise. Structural simplicity, wide range of application and robustness against sampling frequency variation are other salient features of the method. The only limitation as compared with the EPLL system is its slight reduced accuracy (around 3 mHz) under static sinusoidal conditions. Based on simulation studies, performances of the proposed algorithm at different operating conditions have been presented and its accuracy and response time have been compared with the EPLL systems.