DocumentCode
1480671
Title
Art of constructing low-complexity encoders/decoders for constrained block codes
Author
Modha, Dharmendra S. ; Marcus, Brian H.
Author_Institution
IBM Almaden Res. Center, San Jose, CA, USA
Volume
19
Issue
4
fYear
2001
fDate
4/1/2001 12:00:00 AM
Firstpage
589
Lastpage
601
Abstract
A rate p : q block encoder is a dataword-to-codeword assignment from 2p p-bit datawords to 2p q-bit codewords, and the corresponding block decoder is the inverse of the encoder. When designing block encoders/decoders for constrained systems, often, more than 2p codewords are available. In this paper, as our main contribution, we propose efficient heuristic computer algorithms to eliminate the excess codewords and to construct low hardware complexity block encoders/decoders. For (0,4/4) and (0,3/6) PRML constraints, block encoders/decoders generated using the proposed algorithms are comparable in complexity to human-generated encoders/decoders, but are significantly simpler than lexicographical encoders/decoders
Keywords
block codes; computational complexity; decoding; digital magnetic recording; modulation coding; partial response channels; runlength codes; PRML constraints; RLL constraint; block decoder; block encoder; constrained block codes; dataword-to-codeword assignment; excess codewords elimination; heuristic computer algorithms; low-complexity encoders/decoders; magnetic recording; p-bit datawords; partial response maximum likelihood constraint; q-bit codewords; Block codes; CMOS technology; Concrete; Decoding; Hardware; Heuristic algorithms; Logic; Magnetic recording; Modulation coding; Subspace constraints;
fLanguage
English
Journal_Title
Selected Areas in Communications, IEEE Journal on
Publisher
ieee
ISSN
0733-8716
Type
jour
DOI
10.1109/49.920168
Filename
920168
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